Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are useful in many applications including those for generating a compensated percent-of-clock period delay signal. The generation of compensated percent-of-clock period delay signals is, in turn, also useful in many applications. As an example, such a delayed version of a data strobe signal (DQS) is useful for capturing read data (DQ) provided along and edge-aligned with the DQS from a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
The benefits of DDR SDRAMs are well known. Simply put, DDR SDRAMs are probably the most straightforward and least costly approach to doubling memory data bandwidth over the single data rate SDRAMs in common use today.
Read data capture at the memory controller, however, can be a significant challenge using DDR SDRAMs. To assist in read data capture, the DDR SDRAM provides one or more DQS that are edge-aligned with corresponding DQ provided by the DDR SDRAM during a read operation. To capture the data, the memory controller internally delays the received DQS to be within a data valid window, and then captures the DQ using the thus delayed DQS.
The optimal delay for DQS is the average location of the center of the data valid window, taking into account the maximum skew between DQS and DQ (DQSQ″) and the reduced data valid window (DV″) realized at the memory controller. DQSQ″ in this case is the sum of the nominal skew between any data line and its corresponding DQS at the pins of the DDR SDRAM (DQSQ) plus skew additions that are incurred between the DDR SDRAM and the memory controller. For example, in a system where the memory controller is on a separate chip than the DDR SDRAM, such skew additions include board effects between the DDR SDRAM and the chip, and internal routing within the chip. Likewise, DV″ in this case is the nominal DDR SDRAM data valid window at the pins of the DDR SDRAM (DV) reduced by the skew additions.
A percent-of-clock period delay is only one possible approach for implementing the DQS delay for read data capture. Other approaches include using a predetermined absolute delay value or a selectable delay. Each of these implementations, however, is susceptible to process, voltage and temperature variations that may significantly alter the value of their delay line. Such variations may destroy the limited timing budget available for read data capture. Thus, most systems could benefit from a delay implementation that addresses one or more of these error-producing variations.
Delay locked loops (DLLs) have been proposed to compensate for at least reference voltage and temperature variations in the predetermined absolute delay value and selectable delay implementations. A DLL locked to the clock is also thought to be required in a percent-of-clock period delay implementation. However, multiple clock periods are generally required for the DLL to “lock” in these implementations, thereby objectionably adding to the effective read access time in short burst read data captures.